1. Field of the Invention
The present invention relates to a dynamic memory, and more particularly, it relates to a 3-transistor 1-capacitor dynamic memory.
2. Description of the Background Art
Dynamic memories include a 3-transistor 1-capacitor memory, which is provided with memory cells each having three transistors and one capacitor. Such a dynamic memory having 3-transistor 1-capacitor memory cells may be employed as a FIFO (first-in first-out) memory.
FIG. 22 is a block diagram showing the structure of a conventional FIFO memory.
Referring to FIG. 22, this FIFO memory includes a memory cell array 1, a write row pointer 2, a read row pointer 3, an input circuit 4 and an output circuit 6. The memory cell array 1 includes a plurality of memory cells 10 which are arranged in a plurality of rows and a plurality of columns. Each memory cell 10 has three transistors and one capacitor.
Write word lines WWLi (0.ltoreq.i.ltoreq.10) and read word lines RWLi (0.ltoreq.i.ltoreq.10) are provided in correspondence to the respective rows of the memory cell array 1. On the other hand, write bit lines WBLj (0.ltoreq.j.ltoreq.11) and read bit lines RBLj (0.ltoreq.j.ltoreq.11) are provided in correspondence to the respective columns of the memory cell array 1.
The write row pointer 2 and the input circuit 4 select a memory cell for writing data therein. In order to select the memory cell, the write pointer 2 selects a write word line WWLi to be activated, while the input circuit 4 selects a write bit line WLBj for transmitting the data.
The read row pointer 3 and the output circuit 6 select a memory cell whose data must be read out. In order to select the memory cell, the read row pointer 3 selects a read word line RWLi to be activated, while the output circuit 6 selects a read bit line RBLj for transmitting the data.
In the FIFO memory having the aforementioned structure, written data are read in the written order.
The structure of the memory cell array 1 provided in the FIFO memory shown in FIG. 22 is now described in detail. FIG. 23 is a circuit diagram showing the structure of the memory cell array 1 provided in the FIFO memory of FIG. 22 in detail.
Referring to FIG. 23, the plurality of write word lines WWLi and the plurality of read word lines RWLi as well as the plurality of write bit lines WLBj and the plurality of read bit lines RBLj are arranged to intersect with each other.
Source nodes N1 receive source potentials Vdd. First ends of the plurality of read bit lines RBLj are connected to the source nodes N1 through precharge transistors 15 respectively. On the other hand, second ends of the read bit lines RBLj are connected to input terminals of inverters 60 respectively.
Memory cells 10 are arranged on the plurality of intersections between the word lines WWLi and RWLi and the bit lines WBLj and RBLj respectively. Each memory cell 10 includes three N-channel MOS transistors 11, 12 and 13 and one capacitor 14.
Each memory cell 10 has the following structure: A source electrode of the transistor 12 is connected to a ground node N2. The transistor 11 is connected between a gate electrode of the transistor 12 and the write bit line WLBj of the corresponding column. A gate electrode of the transistor 11 is connected to the write word line WWLi of the corresponding row. A node between the gate electrode of the transistor 12 and the transistor 11 is a storage node N3.
The transistor 13 is connected between a drain electrode of the transistor 12 and the read bit line RBLj of the corresponding column. A gate electrode of the transistor 13 is connected to the read word line RWLi of the corresponding row. The capacitor 14 is connected between the ground node N2 and the storage node N3.
Write and read operations of the FIFO memory are now described with reference to the memory cell array shown in FIG. 23.
In the write operation, the potential of the write word line WWLi of the row for writing data is converted to a level "1". In response to this, the transistor 11 provided in the memory cell 10 of this row is turned on. Thus, data of a level "1" or "0" transmitted to the write bit line WBLj is transmitted to the capacitor 14 through the transistor 11. In this case, the storage node N3 is at a level "1" or "0".
In advance of the read operation, on the other hand, the transistors 15 are first turned on in response to a control signal S. Thus, the read bit lines RBLj are precharged at levels "1", and thereafter the transistors 15 are turned off.
Then, the read word line RWLi of the row for reading data is converted to a level "1". The transistor 13 is turned on in response to this.
If the capacitor 14 currently stores data of a level "1", the transistor 12 is in an ON state. Therefore, the read bit line RBLj is connected to the ground node N2 through the transistors 13 and 12. Thus, the potential of the read bit line RBLj is reduced to a ground potential Vss. Consequently, the potential of the read bit line RBLj reaches a level "0".
If the capacitor 14 stores data of a level "0" in an ON state of the transistor 13, on the other hand, the transistor 12 is in an OFF state. Therefore, the read bit line RBLj is not connected with the ground node N2. Consequently, the potential of the read bit line RBLj is maintained at a level "1".
Thus, the level of the potential which is transmitted to each read bit line RBLj is inverted at each inverter 60 and outputted. Therefore, the logical level of a signal which is outputted from each inverter 60 is identical to that of data stored in each capacitor 14.
However, the conventional FIFO memory having the aforementioned structure is problematic in operation, due to first to fifth drawbacks described later.
FIG. 24 is a circuit diagram of each memory cell for illustrating problems in operation of the conventional FIFO memory. In FIG. 24, portions which are common to those in FIG. 23 are denoted by the same reference numerals, to omit redundant description.
Referring to FIG. 24, a coupling capacitance is present between the storage node N3 and each signal line. For example, a coupling capacitance 17 is present between the storage node N3 and the read bit line RBLj. Further, a parasitic capacitance 13 is present between the drain electrode and the gate electrode of the transistor 12. The FIFO memory includes drawbacks in operation, which result from presence of such capacitances.
The first to fifth drawbacks are now described in detail respectively. The first drawback resides in that a potential which is lower than the potential Vdd of the write bit line WBLj by a threshold voltage Vth of the transistor 11 is transmitted to the capacitor 14 when a level "1" is written in the capacitor 14, since the transistor 11 is of the N-channel MOS type. Consequently, the potential of the storage node N3 is Vdd-Vth, also when the potential of the write bit line WBLj is Vdd.
The second drawback resides in that a substrate effect acts in the transistor 11 since the source electrode is at a higher potential than a back gate electrode. Consequently, the potential which is transmitted from the write bit line WBLj to the capacitor 14 through the transistor 11 is further reduced in addition to the potential reduction caused by the first drawback. In more concrete terms, the potential of the storage node N3 is about 1.5 V when the source potential Vdd is 3 V, for example.
The third drawback resides in that the potential of the storage node N3 is increased or reduced by about 0.1 V, for example, by signal interference through the coupling capacitance, such as the coupling capacitance 17, between the storage node N3 and each signal line shown in FIG. 24.
The fourth drawback resides in that the potential of the storage node N3 is increased or reduced by about 0.1 V, for example, by signal interference through the parasitic capacitance 18 shown in FIG. 24.
The fifth drawback resides in that electric charges which are stored in the capacitor 14 leak to reduce the potential of the storage node N3 which is at the level "1".
In the conventional FIFO memory, the following problems result from the first to fifth drawbacks:
When data of a level "1" is stored in the memory cell 10, the storage potential (potential of the storage node N3) is reduced on the basis of the first to fifth drawbacks. Therefore, the value of a current flowing in the transistor 12 is reduced in reading. Consequently, the read rate is disadvantageously reduced.
When data of a level "0" is stored in the memory cell 10, on the other hand, the storage potential is increased on the basis of the third and fourth drawbacks. Thus, a small current flows in the transistor 12 in reading. Consequently, the read bit line RBLj cannot maintain "1", leading to a malfunction.
It may conceivably be possible to suppress these two problems by increasing the capacitance value of the capacitor 14 and the size (drivability) of the transistor 12. In this case, however, the chip area of the memory is disadvantageously increased. Therefore, this countermeasure is improper.
Further, such a FIFO memory is generally used as the so-called dedicated memory which is integrated on the same chip as a logic circuit. In this case, necessary word and bit numbers are varied with applications.
In order to provide a memory which is varied in capacitance value and transistor size as described above by the conventional structure shown in FIG. 23, therefore, it is necessary to change the capacitance value and the transistor size in response to the application. In this case, therefore, a large load is applied in relation to development of the memory.